SPI Troubleshooting

SPI Troubleshooting
FAQs > SPI

A SPI interface provides a simple and common interface to a host processor. Compared to SDIO, it has fewer signals and is unidirectional instead of bidirectional. A SPI interface is specified at a physical layer and as such, the data transfer is less standardised than SDIO. 

Hardware

When selecting a CPU host to interface via SPI to the MM6108, consider the following requirements:

• The host should have a SPI compliant controller with support for SPI mode 0.
• The host must support level-triggered interrupts.
• The host must support full-duplex mode, as this is required by MM6108 for the SPI interface.
  The SPI interface can run at up to 50 MHz clock rate, per the specification.
• The host must support DMA backed transactions if full throughput is required on the SPI bus. Standard SPI can achieve up to 25Mbps at 50MHz, but this will reduce significantly if there is no DMA support. For example, an SPI interface with an 8-byte buffer per transaction might only achieve 2Mbps throughput on the SPI bus.
• The PCB trace length should be kept as short as possible, as extra delay can be caused which will result in lower throughput on the SPI bus.
• The MM6108 launches data on the negative edge. It is preferable to have a SPI host-side that launches on the negative edge, and samples on the positive edge in order to allow for the necessary delays.

The following pins are required for SPI:

Pin	Name	SPI mode function
31	CLK	Clock pin (input)
30	MOSI	Master data out/slave data in
29	MISO	Master data in/slave state out
28	EXT_HOST_SEL	SDIO/SPI/QSPI interface enable strap (tie high)
27	INT	Interrupt pin
26	Unused	Tie high
25	CS	Chip select (active low)

Note: if the waveform shape is abnormal or the timing is irregular, ensure that nothing other than the MM6108 chip and the host CPU is connected on the lines to prevent unintended interference.

Software

Linux-based systems

• The MM6108 SPI interface adheres to the definition in the SDIO 2.0 specification
• The implementation departs from the SDIO specification in two ways:
  
       1. At least 8 clocks with CS deasserted and MOSI held high immediately after reset are required to take the SPI device hardware out of reset and allow it to power up internally.
  
       2. CMD63 can be sent to skip the entire initialization routine of the SDIO specification. This is implemented by the Morse Micro host-side driver, so the host system does not need to handle it. The chip will return an all (8) zeros response to CMD63 indicating success of initialisation.
  
  
• CS needs to be stable after being asserted, orit will prematurely finish the transaction
• The MOSI line should NOT be toggled while waiting for a command response as this may interrupt the transaction
• Sample waveform:
  
  
  
  
• Need to ensure just one byte of clocks is sent and then immediately deassert the MOSI and then start the command transaction
• SPI mode - data clocked in on the rising edge, shifted out on the falling edge (ie SPI Mode 0)

Note: MOSI state doesn't matter if there is no clock running.

FreeRTOS/Microcontroller-based systems

This is quite similar to the above outlined for Linux, but with a couple of differences:

1. Hard reset the device
2. Transmit at least 74 SPI clock pulses (we do this by writing 0xff with CS deasserted 16 times)
3.  Write CMD63
4. If CMD63 was not successful, write CMD0 and go to step 3 above.
5. Read chip ID to validate success.